The present invention is related in general to the field of semiconductor devices and processes and more specifically to thermally enhanced configurations of semiconductor chips having bonds over active circuits and to a method of fabricating these configurations using power distributions integrated into the chip surface.
Removing the thermal heat generated by active components belongs to the most fundamental challenges in integrated circuit technology. Coupled with the ever shrinking component feature sizes and increasing density of device integration is an ever increasing density of power and thermal energy generation. In order, however, to keep the active components at their optimum (low) operating temperatures and speed, this heat must continuously be dissipated and removed to outside heat sinks. This effort, unfortunately, becomes increasingly harder, the higher the energy density becomes.
In known technology, the most effective approach to heat removal focuses on thermal transport through the thickness of the semiconductor chip from the active surface to the passive surface. The passive surface, in turn, is attached to the chip mount pad of a metallic leadframe so that the thermal energy can flow into the chip mount pad of the metallic leadframe. When properly formed, this leadframe can act as a heat spreader to an outside heat sink. In many semiconductor package designs, this implies a leadframe with a portion formed such that this portion protrudes from the plastic device encapsulation; it can thus be directly attached to the outside heat sink. Examples are described in U.S. Pat. Nos. 5,594,234, issued on Jan. 14, 1997 (Carter et al., xe2x80x9cDownset Exposed Die Mount Pad Leadframe and Packagexe2x80x9d) and 6,072,230, issued on Jun. 6, 2000 (Carter et al., xe2x80x9cBending and Forming Method of Fabricating Exposed Leadframes for Semiconductor Devicesxe2x80x9d).
From a standpoint of thermal efficiency, however, these approaches have several shortcomings. First of all, the heat generated by active components must traverse the macroscopic thickness of the semiconductor chip in order to exit from the chip. The heat then faces the thermal barrier of the attach material (typically a polymer) before it can enter the leadframe. Secondly, a technical solution is missing to remove the heat generated by active components directly from the IC into a metallic heat conductor and heat spreader positioned in microscopic proximity to the active component. The usual approach is to first spread the heat through the macroscopic thickness of the molding material (typically an epoxy filled with inorganic particles, a mediocre thermal conductor) and only then into a metallic heat spreader, usually positioned on the surface of the molded package.
The thermal situation is also difficult in a conventional ball-grid (or land-grid) array package. A BGA package generally includes an IC chip, a multi-layer substrate, and a heat spreader. The chip is generally mounted on the heat spreader using a thermally conductive adhesive, such as an epoxy. The heat spreader provides a low resistance thermal path to dissipate thermal energy, and is thus essential for acceptable thermal performance during device operation, necessary for consistent electrical performance. Further, the heat spreader provides structural and mechanical support by acting as a stiffener, adding rigidity to the BGA package, and may thus be referred to as a heat spreader/stiffener.
In contrast to the advantages of the BGA packages, prevailing solutions in BGA packages have lagged in performance characteristics such as power dissipation and the ability to maintain signal integrity in high speed operation necessary for devices such as high speed digital signal processors (DSP) and mixed signal products (MSP) Electrical performance requirements are driving the need to use multi-layer copper-laminated resin substrates (previously ceramic). For higher speeds, flip chip assembly rather than wire bonding has been introduced. Compared to wire bonding within the same package outline, flip chip assembly offers greatly reduced IR drop to the silicon core circuits; significant reduction of power and ground inductances; moderate improvement of signal inductance; moderate difference in peak noise; and moderate reduction in pulse width degradation. An example for some electrical improvements of BGA packages is described in U.S. patent application Ser. No. 09/645,760, filed Aug. 25, 2000 (James et al., xe2x80x9cBall Grid Array Package having Two Ground Levelsxe2x80x9d).
Until now, however, substantial thermal improvements of BGA packages, both of flip-chip and wire bonded chip assemblies, have been lacking. This is especially true for any low-cost thermal advancement, since any cost-adding technical proposal is contrary to the strong market emphasis on total semiconductor device package cost reduction.
An urgent need has therefore arisen to break this vicious cycle and conceive a concept for a low-cost, thermally improved and electrically high performance BGA package structure. In addition, a general semiconductor package structure is needed which based on fundamental physics and design concepts flexible enough to be applied for different semiconductor product families and a wide spectrum of design and assembly variations. It should not only meet high thermal and electrical performance requirements, but should also achieve improvements towards the goals of enhanced process yields and device reliability. Preferably, these innovations should be accomplished using the installed equipment base so that no investment in new manufacturing machines is needed.
In FOURIER""s approach to solving the differential equation of thermal conductance, the thermal flux Q per unit of time is equal to the product of thermal conductivity xcex multiplied by the gradient of temperature T, in the direction of decreasing temperature, and by the area q perpendicular to the temperature gradient:
dQ/dt=xe2x88x92xcexxc2x7(grad T)xc2x7q, 
where Q is the vector (in magnitude and direction) of thermal flux, and xcex is the thermal conductivity, a materials characteristic. The thermal flux is in the direction of the temperature difference and is proportional to the magnitude of that difference.
When, over the length l, the temperature drop is steady and uniform from the high temperature T2 to the low temperature T1, then (grad T) reduces to (T2xe2x88x92T1)/1:
dQ/dt=xe2x88x92xcexxc2x7(q/1)xc2x7(T2xe2x88x92T1). 
xcexxc2x7(q/1) is called the thermal conductance, and the inverse value 1/(xcexxe2x88x92q) is called thermal resistance (in analogy to OHM""s law).
In the present invention, improvements of both xcexxc2x7q and (grad T) are simultaneously provided to enhance the thermal flux vertically away from the heat-generating active components on the active surface of the semiconductor chip.
In addition to this enhanced thermal flux vertically away from the active chip surface, there is the traditional possibility of conducting thermal energy in the opposite direction through the semiconductor material of the chip to its passive surface and beyond into leadframes or other substrates.
The present invention thus provides for optimized thermal performance of integrated circuits, solving one of the most intractable limitations of semiconductor technology.
An integrated circuit (IC) chip has a metal network of electrical power distribution lines which have a thermal conductance at least an order of magnitude greater than underlying thin film electrical interconnects. These lines are deposited on the surface of the chip, located directly over active IC components, and electrically and thermally connected vertically to selected active components below the lines. Electrical conductors are operable to connect the lines to an outside source, and additional electrically non-functional conductors are distributed on the lines, operable to steepen the thermal gradient for thermal flux away from said active components and lines.
The patterned network of bondable and/or solderable metal lines, deposited directly on the IC protective overcoat, provides a number of significant advantages.
The network provides an effective heat-spreader directly over, and close by, the heat-generating IC components.
The network relocates most of the conventional power distribution interconnections from the circuit level to the newly created surface network, thus saving substantial amounts of silicon real estate and permitting shrinkage of the IC area.
The network is electrically and thermally connected vertically to selected active components by metal-filled vias; since these vias can easily be redesigned to other locations, IC designers gain a new degree of design freedom.
The network is deposited and patterned in wafer processing as a sequence of metal layers specifically suited for high thermal conductivity and providing power current and electrical ground potential.
As preferred embodiments of the invention, the lines of the network, with attachable outermost surface, are laid out so that they form pads at locations convenient for attaching xe2x80x9cballsxe2x80x9d of solder or bonding wires.
The network provides attachment locations for additional, electrically non-functional (thermal-only) solder balls (or wire bonds) directly over IC portions of especially high heat generation, thus creating a short path of steepened temperature gradient dissipating the heat flux away from these high-temperature IC portions to (outside) heat sinks.
The network relocates most of the bond pads dedicated to power supply from the conventional alignment along the chip periphery onto the newly created bondable lines, saving substantial additional amounts of silicon real estate, and freeing the bonding machines from their extremely tight connector placement and attachment rules to much more relaxed bonding programs.
In a preferred embodiment of the invention, the chip of a semiconductor device has an integrated circuit fabricated on the first chip surface (xe2x80x9cactivexe2x80x9d surface) the circuit comprises active components, at least one metal layer, and a protection by a mechanically strong, electrically insulating overcoat which has a plurality of metal-filled vias to contact said at least one metal layer, and a plurality of windows to expose circuit contact pads. The chip further has a stack of electrically conductive films deposited on the overcoat; the films are patterned into a network of lines substantially vertically over the active components. The stack has a bottom-most film in contact with the vias, at least one stress-absorbing film, and an outermost film which is non-corrodible and metallurgically attachable. The network is patterned to spread thermal energy and distribute power current and ground potential.
Electrical conductors (for example, solder balls) are connecting the network lines to an outside electrical source, and additional electrically non-functional (thermal-only) conductors (for example, solder balls) are distributed on the lines for thermal flux away from the lines to an outside heat sink.
In another embodiment of the invention, a plurality of windows is opened in the chip overcoat to expose circuit contact pads. A leadframe is provided, which has a chip mount pad, a first plurality of segments providing electrical power and ground, and a second plurality of segments providing electrical signals. The second (xe2x80x9cpassivexe2x80x9d) surface of the chip is attached to the mount pad of the leadframe. Electrical and thermal conductors (for example, bonding wires) connect the network of lines with the first plurality of segments. Electrical conductors (for example, bonding wires) connect the chip contact pads with the second plurality of segments.
It is an aspect of the present invention to reduce the cost of IC chips by reducing the silicon areas consumed by the circuit power distribution lines, as well as by the chip contact pads for power connections.
Another aspect of the invention is to gain a new degree of circuit design flexibility by enabling the power connection to active components in geometrically shortest path and a no penalty for redesign.
Another aspect of the invention is to improve assembly manufacturability by relaxing the tight placement rules for solder bonding and ball attachment in wire bonding.
Another aspect of the present invention is to advance the process and operation reliability of semiconductor probing, and solder-attached and wire bonded assemblies by providing the pad metal layers, and insulating layers separating the contact pad and the circuit, in thicknesses sufficient to reliably absorb mechanical, thermal and impact stresses.
Another aspect of the invention is to eliminate restrictions on the processes of probing and of solder attachment and wire bonding, thus minimizing the risks of inflicting cracking damage even to very brittle circuit dielectrics.
Another aspect of the invention is to provide design and layout concepts and process methods which are flexible so that they can be applied to many families of semiconductor IC products, and are general, so that they can be applied to several generations of products.
Another aspect of the invention is to provide a low-cost and high-speed process for fabrication, testing and assembly.
Another aspect of the invention is to use only design concepts and processes most commonly used and accepted in the fabrication of IC devices, thus avoiding the cost of new capital investment and using the installed fabrication equipment base.
These aspects have been achieved by the teachings of the invention concerning design concepts and process flow suitable for mass production. Various modifications have been successfully employed to satisfy different selections of product geometries and materials.
The technical advances represented by the invention, as well as the objects thereof, will become apparent from the following description of the preferred embodiments of the invention, when considered in conjunction with the accompanying drawings and the novel features set forth in the appended claims.